High-performance, high-gain, submicrometer GaInAs JFETs

The microwave performance of short-gate JFETs, made on GaInAs lattice matched on InP, realized by n-type ion implantation and zinc diffusion, is reported. A typical structure consists of an undoped 0.4-μm-thick GaInAs layer grown on an 0.1-μm-thick InP buffer layer using trichloride vapor-phase epitaxy. The n-type doping is obtained by Si ion implantation. The p-n junction is obtained by zinc diffusion into the implanted layer. 0.55 or 0.65 μm TiPtAu gates are defined by conventional lithography. Drain source contacts are aligned with respect to the gate. Typical transconductances of about 200-240 mS/mm have been measured between -0.5 and -1.5 V, and gate source capacitances are in the range 0.5-0.7 pF/mm at V_gs=-1 V. Extremely high maximum available gains (MAG) up to 16.7 dB at 12 GHz and 13 dB at 18 GHz have been observed together with best values for MSG of 13.1 dB at 20 GHz. The current cutoff frequency is as high as 53 GHz for 0.55-μm gates, and the maximum frequency is up to 110 GHz. These results are, to the authors´ knowledge, the best ever reported for GaInAs JFETs