A step-down boosted-wordline scheme for 1-V battery-operated fast SRAM´s

Author

Morimura, Hiroki ; Shibata, Nobutaro

Author_Institution

Integrated Inf. & Energy Syst. Labs., NTT, Kanagawa, Japan

Volume

33

Issue

8

fYear

1998

fDate

8/1/1998 12:00:00 AM

Firstpage

1220

Lastpage

1227

Abstract

Fast and low-power circuit techniques for battery-operated low-voltage SRAM´s are described. To shorten the read access time with low power dissipation, the step-down boosted-wordline scheme, which is combined with current-sense amplifiers, is proposed. Boosting a selected-wordline voltage shortens the bitline delay before the stored data are sensed. The power dissipation while selecting a wordline is suppressed by stepping down the selected-wordline potential. Moreover, to reduce the standby power, a switched-capacitor-type boosted-pulse generator, which is controlled by an address transition detection (ATD) signal, is used. A 61 kword×16-bit organization SRAM test chip was fabricated using the 0.5-μm multithreshold-voltage CMOS (MTCMOS) process. The power dissipation in the memory array is reduced to 57% (1 mW) at 10 kHz operation in comparison with the conventional boosted-wordline scheme

Keywords

CMOS memory circuits; SRAM chips; 0.5 micron; 1 V; 1 mW; 10 MHz; SC boosted-pulse generator; address transition detection signal; battery-operated fast SRAM; current-sense amplifiers; low-power circuit techniques; low-voltage static RAM; multithreshold-voltage CMOS process; read access time; selected-wordline voltage boosting; standby power reduction; step-down boosted-wordline scheme; switched-capacitor-type; Boosting; Circuits; Delay; Power dissipation; Power generation; Random access memory; Signal detection; Signal generators; Standby generators; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.705360

Filename

705360