DocumentCode :
1409451
Title :
Modeling and performance analysis of cluster tools using Petri nets
Author :
Srinivasan, R.S.
Author_Institution :
Appl. Mater. Inc., Austin, TX, USA
Volume :
11
Issue :
3
fYear :
1998
fDate :
8/1/1998 12:00:00 AM
Firstpage :
394
Lastpage :
403
Abstract :
The performance of cluster tools is gaining ever-increasing importance as the semiconductor industry migrates to larger wafer sizes, and smaller device geometries. Customers demand higher throughput-to-footprint ratios for semiconductor equipment. Cluster tool throughput is the outcome of complex interactions of various subsystems, and there is a critical need for appropriate tools that aid in understanding these interactions, and their effects on throughput. Current methods for throughput analysis are not very well oriented toward understanding the dynamics in cluster tool processing. In this paper we present a procedure to model cluster tools using Petri nets. These models help designers to comprehend the flow of wafers during processing. While Petri nets have been used extensively in the modeling and analysis of diverse manufacturing processes/systems, this to the best of our knowledge is the first attempt to specifically model cluster tools. A state cycle analysis is discussed next; this method enables equipment designers to extract steady state throughput information, as well as understand the interplay of subsystems during the wafer Row. Two example configurations are used to illustrate Petri net-based model building and analysts. These two examples encompass a variety of design features found in the industry today, e.g., sequential and parallel processing, single and dual end effector robots, anticipatory and simple scheduling
Keywords :
Petri nets; cluster tools; semiconductor process modelling; Petri net; cluster tool; dual end effector robot; equipment design; manufacturing system; modeling; parallel processing; performance analysis; scheduling; semiconductor industry; sequential processing; single end effector robot; state cycle analysis; throughput-to-footprint ratio; Data mining; Design methodology; Electronics industry; Geometry; Information analysis; Manufacturing processes; Performance analysis; Petri nets; Semiconductor device modeling; Throughput;
fLanguage :
English
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
0894-6507
Type :
jour
DOI :
10.1109/66.705374
Filename :
705374
Link To Document :
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