Partial scan design based on levelised combinational structure

To overcome the large hardware overhead attendant in the full scan design, the concept of partial scan design has emerged with the virtue of less area and testability close to full scan. A `combinational structure´ has been developed to avoid the use of a sequential test generator. But test patterns shifted on the scan register have to be held for a sequential depth period upon the aid of the dedicated HOLD circuit. In this paper a new levelised structure is introduced aiming to exclude the need for an extra HOLD circuit. The time to stimulate each scan latch is uniquely determined on this structure, hence each test pattern can be applied by scan shifting and then pulsing a system clock like the full scan, but with many fewer scan flip-flops. Experimental results show that some sequential circuits are levelised by just scanning self-loop flip-flops