• DocumentCode
    1410698
  • Title

    Parallelism exploitation in superscalar multiprocessing

  • Author

    Lu, N.P. ; Chung, C.P.

  • Author_Institution
    Dept. of Comput. & Inf. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan
  • Volume
    145
  • Issue
    4
  • fYear
    1998
  • fDate
    7/1/1998 12:00:00 AM
  • Firstpage
    255
  • Lastpage
    264
  • Abstract
    To exploit more parallelism in programs, superscalar multiprocessor systems, which exploit both fine-grained and coarse-grained parallelism, have been the trend in designing high-speed computing systems. Recently, the authors have developed a simulator for evaluating superscalar multiprocessor systems. This simulator models both a superscalar processor that can exploit instruction-level parallelism, and a shared-memory multiprocessor system that can exploit task-level parallelism. This simulator was used to run four applications chosen from the SPLASH-2 benchmark suite, and collected some performance data to investigate the parallelism exploitation capability of the superscalar multiprocessor systems in various configurations. It was observed that the instruction-level and task-level parallelism in programs can be exploited well by a moderate degree of superscalar processing and a high degree of multiprocessing. For example, the speedup of a 32-way multiprocessor with eightissue processors can be over 200 relative to a single-issue uniprocessor
  • Keywords
    digital simulation; multiprocessing systems; reduced instruction set computing; SPLASH-2 benchmark suite; high-speed computing systems; instruction-level parallelism; parallelism exploitation; shared-memory multiprocessor system; simulator; superscalar multiprocessing;
  • fLanguage
    English
  • Journal_Title
    Computers and Digital Techniques, IEE Proceedings -
  • Publisher
    iet
  • ISSN
    1350-2387
  • Type

    jour

  • DOI
    10.1049/ip-cdt:19981955
  • Filename
    705689