DocumentCode :
1410704
Title :
Fast algorithm for modular reduction
Author :
Kop, Q.K. ; Hung, C.Y.
Author_Institution :
Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA
Volume :
145
Issue :
4
fYear :
1998
fDate :
7/1/1998 12:00:00 AM
Firstpage :
265
Lastpage :
271
Abstract :
The paper presents an algorithm for computing the residue R=X mod M. The algorithm is based on a sign estimation technique that estimates the sign of a number represented by a carry-sum pair produced by a carry save adder. Given the (n+k)-bit X and the n-bit M, the modular reduction algorithm computes the n-bit residue R in O(k+log n) time, and is particularly useful when the operand size is large. We also present a variant of the algorithm that performs modular multiplication by interleaving the shift-and-add and the modular reduction steps. The modular multiplication algorithm can be used to obtain efficient VLSI implementations of exponentiation cryptosystems
Keywords :
adders; digital arithmetic; VLSI implementations; carry save adder; carry-sum pair; exponentiation cryptosystems; modular multiplication; modular reduction; sign estimation technique;
fLanguage :
English
Journal_Title :
Computers and Digital Techniques, IEE Proceedings -
Publisher :
iet
ISSN :
1350-2387
Type :
jour
DOI :
10.1049/ip-cdt:19982091
Filename :
705690
Link To Document :
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