• DocumentCode
    1411197
  • Title

    Design of cache test hardware on the HP PA8500

  • Author

    Bralich, J. ; Fleischman, Jay

  • Author_Institution
    Hewlett-Packard Co., Fort Collins, CO, USA
  • Volume
    15
  • Issue
    3
  • fYear
    1998
  • Firstpage
    58
  • Lastpage
    63
  • Abstract
    Refinements to testing strategies for earlier microprocessor on-chip caches led to fast, efficient characterization and debugging of the smaller geometry PA8500 cache
  • Keywords
    Hewlett Packard computers; cache storage; integrated circuit testing; HP PA8500; PA8500 cache; cache test hardware; on-chip caches; Computational geometry; Debugging; Hardware; Legged locomotion; Microprocessors; Performance evaluation; Production; Random sequences; Read-write memory; Testing;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.706034
  • Filename
    706034