Title :
Integrated Batteryless Electron Timer
Author :
Watanabe, Hiroshi ; Ushijima, Tomomi ; Hagiwara, Norio ; Okada, Chiomi ; Tanabe, Takeshi
Author_Institution :
Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
3/1/2011 12:00:00 AM
Abstract :
From the viewpoint of information security, the semiconductor timing devices are reviewed, and a promising cell with floating gate (FG) is proposed as an integrated batteryless electron timer. The first issue is the difficulty in the timing precision, which is related to the trap-detrapping phenomena in the tunnel oxide between the FG and the silicon surface. The basic idea to resolve this issue is to monitor the trap-free cells among a plurality of prepared cells. The integrated batteryless electron timer is composed of a plurality of single-polysilicon-type solid-state aging devices that are connected in parallel. The first sample is fabricated in a standard complementary metal-oxide-semiconductor process, and the measurements clearly exhibit the first evidence that we succeeded to remove the trap-detrapping-related fluctuation in the ticking operation. The resultant secondary issues on the precision, i.e., the manufacturing fluctuation (subjecting to the central-limit theorem) and the temperature dependence, are also briefly discussed.
Keywords :
CMOS integrated circuits; timing circuits; complementary metal-oxide-semiconductor process; floating gate; information security; integrated batteryless electron timer; semiconductor timing device; silicon surface; single-polysilicon-type solid-state aging device; trap-detrapping phenomena; trap-detrapping-related fluctuation removal; trap-free cell monitoring; tunnel oxide; Batteryless; communication network; encryption; local trap; solid-state aging device (SSAD); timing device;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2010.2096226