Title :
Corrections to “Predictive 3-D Modeling of Parasitic Gate Capacitance in Gate-all-Around Cylindrical Silicon Nanowire MOSFETs” [Oct 11 3379-3387]
Author :
Zou, Jingxin ; Xu, Qi ; Luo, JianChao ; Wang, Ruiqi ; Huang, R. ; Wang, Yannan
Author_Institution :
Institute of Microelectronics, Peking University, Beijing, China
fDate :
3/1/2012 12:00:00 AM
Abstract :
In the above titled paper (ibid., vol. 58, no. 10. pp. 3379-3387, Oct. 2011), there were several typo errors or missing symbols. Corrections are presented here.
Keywords :
Analytical models; Capacitance; MOSFETs; Nanowires; Parasitic capacitance;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2011.2178417
