Single-Event Transient Measurements in nMOS and pMOS Transistors in a 65-nm Bulk CMOS Technology at Elevated Temperatures

Author

Gadlage, Matthew J. ; Ahlbin, Jonathan R. ; Narasimham, Balaji ; Bhuva, Bharat L. ; Massengill, Lloyd W. ; Schrimpf, Ronald D.

Author_Institution

NAVSEA Crane, Crane, IN, USA

Volume

11

Issue

1

fYear

2011

fDate

3/1/2011 12:00:00 AM

Firstpage

179

Lastpage

186

Abstract

In this paper, heavy-ion-induced single-event transient (SET) pulsewidths measured in a 65-nm bulk CMOS technology at temperatures ranging from 25°C to 100°C with an autonomous SET capture circuit are presented. The experimental results for the SETs induced in two different inverter chain circuits indicate an increase in the average SET pulsewidth as a function of the operating temperature. Unique SET test structures were also designed to differentiate between SETs induced in an nMOS transistor and those induced in a pMOS transistor. The SET widths induced in a pMOS transistor increase more with temperature than the SETs induced in an nMOS transistor.

Keywords

CMOS integrated circuits; MOSFET; invertors; autonomous SET capture circuit; bulk CMOS technology; heavy-ion-induced SET pulsewidths; inverter chain circuits; nMOS transistors; pMOS transistors; single-event transient measurements; size 65 nm; temperature 25 degC to 100 degC; Pulsewidth; radiation environment; single event; single-event transient (SET); soft error; soft error rate (SER); temperature;

fLanguage

English

Journal_Title

Device and Materials Reliability, IEEE Transactions on

Publisher

ieee

ISSN

1530-4388

Type

jour

DOI

10.1109/TDMR.2010.2102354

Filename

5676187