• DocumentCode
    1413899
  • Title

    Design of an FPGA-Based Algorithm for Real-Time Solutions of Statistics-Based Positioning

  • Author

    DeWitt, Don ; Johnson-Williams, Nathan G. ; Miyaoka, Robert S. ; Li, Xiaoli ; Lockhart, Cate ; Lewellen, Tom K. ; Hauck, Scott

  • Author_Institution
    Dept. of Electr. Eng., Univ. of Washington, Seattle, WA, USA
  • Volume
    57
  • Issue
    1
  • fYear
    2010
  • Firstpage
    71
  • Lastpage
    77
  • Abstract
    We report on the implementation of an algorithm and hardware platform to allow real-time processing of the statistics-based positioning (SBP) method for continuous miniature crystal element (cMiCE) detectors. The SBP method allows an intrinsic spatial resolution of ~1.6 mm FWHM to be achieved using our cMiCE design. Previous SBP solutions have required a postprocessing procedure due to the computation and memory intensive nature of SBP. This new implementation takes advantage of a combination of algebraic simplifications, conversion to fixed-point math, and a hierarchal search technique to greatly accelerate the algorithm. For the presented seven stage, 127 × 127 bin LUT implementation, these algorithm improvements result in a reduction from > 7 × 106 floating-point operations per event for an exhaustive search to < 5 × 103 integer operations per event. Simulations show nearly identical FWHM positioning resolution for this accelerated SBP solution, and positioning differences of <0.1 mm from the exhaustive search solution. A pipelined field programmable gate array (FPGA) implementation of this optimized algorithm is able to process events in excess of 250 K events per second, which is greater than the maximum expected coincidence rate for an individual detector. In contrast with all detectors being processed at a centralized host, as in the current system, a separate FPGA is available at each detector, thus dividing the computational load. These methods allow SBP results to be calculated in real-time and to be presented to the image generation components in real-time. A hardware implementation has been developed using a commercially available prototype board.
  • Keywords
    algebra; field programmable gate arrays; floating point arithmetic; image processing equipment; logic design; optimisation; pipeline arithmetic; positron emission tomography; statistical analysis; FPGA-based algorithm; LUT implementation; PET scanners; algebraic simplifications; continuous miniature crystal element detectors; exhaustive search solution; fixed-point math; floating-point operations; hardware implementation; hierarchal search technique; image generation components; optimized algorithm; pipelined field programmable gate array; postprocessing procedure; real-time processing; statistics-based positioning; Acceleration; Algorithm design and analysis; Detectors; Event detection; Field programmable gate arrays; Hardware; Image generation; Sensor arrays; Spatial resolution; Table lookup; Continuous crystal; PET detector; field programmable gate array (FPGA);
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/TNS.2009.2030581
  • Filename
    5409998