DocumentCode :
1413915
Title :
Intel´s 80960: an architecture optimized for embedded control
Author :
Ryan, David P.
Author_Institution :
Intel Corp., Chandler, AZ, USA
Volume :
8
Issue :
3
fYear :
1988
fDate :
6/1/1988 12:00:00 AM
Firstpage :
63
Lastpage :
76
Abstract :
Important features and capabilities of the 80960 are briefly examined, and an overview of its architecture is given. A detached discussion is presented of the register model, core instruction set, register operations, memory operations, control operations instruction cache, user-supervisor protection, interrupts, faults, and debug support.<>
Keywords :
computer architecture; instruction sets; microprocessor chips; Intel 80960 processor; control operations instruction cache; core instruction set; debug support; embedded control; interrupts; memory operations; register model; register operations; user-supervisor protection; Clocks; Design optimization; Memory management; Microarchitecture; Optimizing compilers; Out of order; Pipelines; Reduced instruction set computing; Registers; Silicon;
fLanguage :
English
Journal_Title :
Micro, IEEE
Publisher :
ieee
ISSN :
0272-1732
Type :
jour
DOI :
10.1109/40.541
Filename :
541
Link To Document :
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