• DocumentCode
    1414200
  • Title

    Design of 3:1 multiplexer standard cell

  • Author

    Corsonello, P. ; Perri, S. ; Kantabutra, V.

  • Author_Institution
    Dept. of Comput. Sci., Univ. of Reggio Calabria, Italy
  • Volume
    36
  • Issue
    24
  • fYear
    2000
  • fDate
    11/23/2000 12:00:00 AM
  • Firstpage
    1994
  • Lastpage
    1995
  • Abstract
    A new VLSI 3:1 multiplexer is presented. The proposed circuit is based on a double controlled tri-state buffer. A custom cell which can easily be added to the AMS 0.6 μm CMOS standard cell library has been developed. The new cell shows a propagation delay of ~780 ps and dissipates 5.2 μW/MHz
  • Keywords
    CMOS logic circuits; VLSI; integrated circuit design; logic design; 0.6 micron; 780 ps; AMS CMOS standard cell library; VLSI 3:1 multiplexer; custom cell; double controlled tri-state buffer; multiplexer standard cell design; propagation delay; three-input multiplexer scheme;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20001426
  • Filename
    888278
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1414200