Breakdown in bulk field-effect transistors

Avalanche multiplication effects in the pinchoff region of a bulk field-effect transistor are examined. A silicon planar field-effect structure fabricated by diffusing an upper ptype gate into an epitaxial ntype layer located on a ptype substrate is considered as an example. The division of the total gate-channel potential into a portion which is developed in the drain region and a portion which is developed in the channel of the device as suggested in the literature is shown to be necessary to reconcile theoretical computations and experimental breakdown measurements for a planar structure.