DocumentCode
1415222
Title
Low-power technique of scan-based design for test
Author
Xu, Lei ; Sun, Yihe ; Chen, Hongyi
Author_Institution
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Volume
36
Issue
23
fYear
2000
fDate
11/9/2000 12:00:00 AM
Firstpage
1920
Lastpage
1921
Abstract
Details of an advanced scan tree structure for test power reduction, and the novel approach of rate of bit propagation which is used to estimate power consumption, are presented. Test power consumptions for advanced scan tree and traditional scan chains are compared
Keywords
boundary scan testing; design for testability; digital integrated circuits; integrated circuit testing; logic testing; low-power electronics; advanced scan tree structure; bit propagation rate; low-power technique; power consumption estimation; scan chains; scan-based DFT; scan-based design for test; test power reduction;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20001373
Filename
888655
Link To Document