DocumentCode
1415236
Title
Fast VLSI motion estimator based on bit plane matching
Author
Ko, Y.-K. ; Kim, H.-G. ; Oh, H.-C. ; Ko, S.J.
Author_Institution
Dept. of Electron. Eng., Korea Univ., Seoul, South Korea
Volume
36
Issue
23
fYear
2000
fDate
11/9/2000 12:00:00 AM
Firstpage
1923
Lastpage
1924
Abstract
A fast VLSI motion estimator based on bit plane matching is proposed. The motion estimator employs a pair of processing cores that calculate the motion vector concurrently. By controlling the data flow in a systolic fashion using internal shift registers of the processing cores, the local memory (SRAM) is discarded to reduce the time overhead for accessing the local memory and utilise lower-cost fabrication technology
Keywords
CMOS digital integrated circuits; VLSI; digital signal processing chips; high-speed integrated circuits; motion estimation; parallel architectures; 0.6 micron; 54 MHz; DSP chip; bit plane matching; block matching algorithm; concurrent motion vector calculation; core internal shift registers; data flow control; fast VLSI motion estimator; processing core pair; triple metal CMOS process;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20001342
Filename
888657
Link To Document