Power-aware microarchitecture: design and modeling challenges for next-generation microprocessors

Author

Brooks, David M. ; Bose, Pradip ; Schuster, Stanley E. ; Jacobson, Hans ; Kudva, Prabhakar N. ; Buyuktosunoglu, Alper ; Wellman, John-David ; Zyuban, Victor ; Gupta, Manish ; Cook, Peter W.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

20

Issue

6

fYear

2000

Firstpage

26

Lastpage

44

Abstract

The ability to estimate power consumption during early-stage definition and trade-off studies is a key new methodology enhancement. Opportunities for saving power can be exposed via microarchitecture-level modeling, particularly through clock-gating and dynamic adaptation. In this paper we describe the approach of using energy-enabled performance simulators in early design. We examine some of the emerging paradigms in processor design and comment on their inherent power-performance characteristics

Keywords

logic design; microprocessor chips; clock-gating; dynamic adaptation; energy-enabled performance simulators; next-generation microprocessors; power consumption estimation; power-aware microarchitecture; Clocks; Costs; Energy consumption; Frequency; Microarchitecture; Microprocessors; Power dissipation; Process design; Switching loss; Voltage;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/40.888701

Filename

888701