Title :
SEU Tolerant Memory Using Error Correction Code
Author :
She, Xiaoxuan ; Li, N. ; Jensen, D. Waileen
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Abstract :
With decreasing circuit lithography dimensions and increasing memory densities, an SEU may affect multiple adjacent memory cells. This paper presents an SEU hardened memory using error correction code that can correct single errors, double-adjacent errors, triple-adjacent errors and double-almost-adjacent errors. The proposed memory introduces small area, power and delay overheads.
Keywords :
SRAM chips; error correction codes; lithography; SEU hardened memory; SEU tolerant memory; circuit lithography dimensions; double-adjacent errors; double-almost-adjacent errors; error correction code; memory densities; multiple adjacent memory cells; single errors; triple-adjacent errors; Convolution; Delay; Error correction codes; Logic gates; Random access memory; Single event upset; Transistors; Error correction code; hardened by design; single event upset (SEU);
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2011.2176513
