Competitive learning algorithms and neurocomputer architecture

Author

Card, H.C. ; Rosendahl, G.K. ; McNeill, D.K. ; McLeod, R.D.

Author_Institution

Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada

Volume

47

Issue

8

fYear

1998

fDate

8/1/1998 12:00:00 AM

Firstpage

847

Lastpage

858

Abstract

This paper begins with an overview of several competitive learning algorithms in artificial neural networks, including self-organizing feature maps, focusing on properties of these algorithms important to hardware implementations. We then discuss previously reported digital implementations of these networks. Finally, we report a reconfigurable parallel neurocomputer architecture we have designed using digital signal processing chips and field-programmable gate array devices. Communications are based upon a broadcast network with FPGA-based message preprocessing and postprocessing. A small prototype of this system has been constructed and applied to competitive learning in self-organizing maps. This machine is able to model slowly-varying nonstationary data in real time

Keywords

digital signal processing chips; neural net architecture; parallel architectures; self-organising feature maps; unsupervised learning; FPGA-based message preprocessing; artificial neural networks; competitive learning algorithms; digital signal processing chips; field-programmable gate array devices; hardware implementations; neurocomputer architecture; nonstationary data; postprocessing; reconfigurable parallel neurocomputer architecture; self-organizing feature maps; Artificial neural networks; Clustering algorithms; Computer architecture; Concurrent computing; Digital signal processing chips; Field programmable gate arrays; Neural network hardware; Prototypes; Signal design; Signal processing algorithms;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.707586

Filename

707586