A Novel Short-Channel Model for Threshold Voltage of Trigate MOSFETs With Localized Trapped Charges

Author

Chiang, Te-Kuang

Author_Institution

Dept. of Electr. Eng., Nat. Univ. of Kaohsiung, Kaohsiung, Taiwan

Volume

12

Issue

2

fYear

2012

fDate

6/1/2012 12:00:00 AM

Firstpage

311

Lastpage

316

Abstract

Based on the scaling equation and perimeter-weighted-sum approach, a novel short-channel threshold voltage model for the trigate (TG) MOSFETs with localized interface trapped charges is developed by considering the effects of equivalent oxide charges on the flatband voltage. The model shows how the positive/negative trapped charges, silicon thickness, silicon width, oxide thickness, and normalized damaged zone affect the threshold voltage behavior. The model is verified by the 3-D device simulator “DESSIS” and can be efficiently used to investigate the hot-carrier-induced threshold voltage degradation of the advanced TG charge-trapped memory device.

Keywords

MOSFET; semiconductor device models; 3D device simulator; DESSIS; advanced TG charge-trapped memory device; equivalent oxide charges; flatband voltage; hot-carrier-induced threshold voltage degradation; localized interface trapped charges; normalized damaged zone; perimeter-weighted-sum approach; positive-negative trapped charges; scaling equation; short-channel threshold voltage model; trigate MOSFET; Degradation; Logic gates; MOSFETs; Mathematical model; Silicon; Solid modeling; Threshold voltage; Hot-carrier-induced threshold voltage; perimeter-weighted-sum approach; scaling equation; trigate (TG) MOSFETs;

fLanguage

English

Journal_Title

Device and Materials Reliability, IEEE Transactions on

Publisher

ieee

ISSN

1530-4388

Type

jour

DOI

10.1109/TDMR.2011.2182198

Filename

6125239