Title :
A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique
Author :
Chen, Xin ; Yang, Jun ; Shi, Long-xing
Author_Institution :
Nat. ASIC Syst. Eng. Res. Center, Southeast Univ., Nanjing, China
fDate :
5/1/2011 12:00:00 AM
Abstract :
A fast locking all-digital phase-locked loop (ADPLL) via feed-forward compensation technique is proposed in this paper. The implemented ADPLL has two operation modes which are frequency acquisition mode and phase acquisition mode. In frequency acquisition mode, the ADPLL achieves a fast frequency locking via the proposed feed-forward compensation algorithm. In phase acquisition mode, the ADPLL achieves a finer phase locking. To verify the proposed algorithm and architecture, the ADPLL design is implemented by SMIC 0.18-μm 1P6M CMOS technology. The core size of the ADPLL is 582.2 μm * 343 μm. The frequency range of the ADPLL is from 4 to 416 MHz. The measurement results show that the ADPLL can achieve a frequency locking in two reference cycles when locking to 376 MHz. The corresponding power consumption is 11.394 mW.
Keywords :
CMOS integrated circuits; digital phase locked loops; feedforward; frequency locked loops; SMIC 1P6M CMOS technology; all-digital phase-locked loop; feed-forward compensation; frequency 4 MHz to 416 MHz; frequency acquisition mode; frequency locking; operation modes; phase acquisition mode; power 11.394 mW; size 0.18 mum; Bandwidth; CMOS technology; Clocks; Digital control; Digital filters; Energy consumption; Feedforward systems; Frequency; Oscillators; Phase locked loops; All-digital phase-locked loop (ADPLL); digitally controlled oscillator (DCO); feed-forward compensation technique; frequency divider;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2009.2039971
