SiGe BiCMOS 3.3-V clock and data recovery circuits for 10-Gb/s serial transmission systems

Author

Meghelli, Mounir ; Parker, Ben ; Ainspan, Herschel ; Soyuer, Mehmet

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

35

Issue

12

fYear

2000

Firstpage

1992

Lastpage

1995

Abstract

Two fully monolithic clock and data recovery (CDR) circuits for serial optical fiber links are presented. One CDR is targeting SONET OC-192 application while the other is a possible 10-GigaBit Ethernet application using 8B/10B coded data. The ICs are fabricated in a SiGe BiCMOS technology with a 45-GHz cut-off frequency. The CDRs extract a full rate clock and recover data from a random input bit stream. Each IC integrates a novel self-correcting phase detector, a delay-interpolating ring voltage-controlled oscillator, and a lock-to-reference loop for frequency acquisition. High-speed operation, low time jitter, and large jitter tolerance are the main features of the circuits. Each macro dissipates about 320 mW from 3.3-V supply.

Keywords

BiCMOS integrated circuits; Ge-Si alloys; SONET; optical fibre LAN; optical fibre networks; phase detectors; semiconductor materials; synchronisation; timing jitter; voltage-controlled oscillators; 10 Gbit/s; 3.3 V; 320 mW; 45 GHz; BiCMOS; CDR; Ethernet application; SONET OC-192 application; SiGe; clock and data recovery circuits; cut-off frequency; delay-interpolating ring voltage-controlled oscillator; frequency acquisition; high-speed operation; jitter tolerance; lock-to-reference loop; random input bit stream; self-correcting phase detector; serial optical fiber links; serial transmission systems; time jitter; BiCMOS integrated circuits; Clocks; Cutoff frequency; Data mining; Ethernet networks; Germanium silicon alloys; Jitter; Optical fibers; SONET; Silicon germanium;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.890314

Filename

890314