DocumentCode
1417577
Title
Parasitic-compensated switched-capacitor delay lines
Author
Franca, J.E.
Volume
24
Issue
7
fYear
1988
fDate
3/31/1988 12:00:00 AM
Firstpage
377
Lastpage
379
Abstract
Describes a systematic approach to the design of passive parasitic-compensated switched capacitor (SC) delay lines employing well known SC branches. Such delay lines are important building blocks for the implementation of high frequency FIR SC decimators and interpolators with high selectivity amplitude responses
Keywords
delay lines; signal processing; switched capacitor networks; building blocks; employing well known SC branches; high frequency FIR SC decimators; high selectivity amplitude responses; interpolators; passive parasitic-compensated switched-capacitor delay lines; systematic design approach; video signal processing;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
Filename
5680
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