DocumentCode
1417821
Title
Numerical and experimental comparison of vertical DMOSFET and UMOSFET
Author
Temple, V.A.K. ; Baliga, B. Jayant
Volume
35
Issue
12
fYear
1988
fDate
12/1/1988 12:00:00 AM
Firstpage
2459
Lastpage
2460
Abstract
A numerical analysis has been performed to evaluate the relative performance of DMOS and UMOS power FETs based on a two-dimensional analytical approach. Since termination technology can achieve a near-ideal breakdown voltage for a given substrate resistivity and thickness, the breakdown voltage is determined by the intrinsic geometry of the unit cell in the vertical power MOSFETs (DMOSFET and UMOSFET). The authors analyse the on-resistance value each structure can offer while satisfying a specific blocking voltage requirement is given
Keywords
insulated gate field effect transistors; power transistors; semiconductor device models; 2D model; DMOS power FET; DMOSFET; UMOS power FETs; UMOSFET; blocking voltage; experimental comparison; intrinsic geometry; near-ideal breakdown voltage; numerical analysis; on-resistance; substrate resistivity; termination technology; unit cell; vertical power MOSFETs; Capacitance; Conductivity; Doping; Geometry; Numerical analysis; Performance analysis; Poisson equations; Research and development; Semiconductor process modeling; Voltage;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.8904
Filename
8904
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