TDMOS-an ultra-low on-resistance power transistor

Author

Mukherjee, Sayan ; Kim, Marn-Go ; Tsou, L. ; Simpson, Michael

Author_Institution

North American Philips Corp., Briarcliff Manor, NY

Volume

35

Issue

12

fYear

1988

fDate

12/1/1988 12:00:00 AM

Firstpage

2459

Abstract

The authors report a trench sidewall channel double-diffused MOS transistor (TDMOS) with specific on-resistance of active <80 mΩ-mm², the lowest value reported to date. A novel five-mask process was used to fabricate the trench sidewall channel MOS transistor. The specific on-resistance of a typical device for active area is 75 mΩ-mm², with a threshold voltage of 2.8 V and subthreshold slope of 195 mV/decade. The drain-to-source breakdown voltage is 52 V. Two-dimensional simulation of electric field in the off-state and carrier flow in the on-state has been carried out, and design considerations have been determined

Keywords

insulated gate field effect transistors; power transistors; 2.8 V; 2D simulation; 52 V; TDMOS; carrier flow; design considerations; drain-to-source breakdown voltage; electric field; five-mask process; specific on-resistance; subthreshold slope; threshold voltage; trench sidewall channel DMOS; trench sidewall channel MOS transistor; trench sidewall channel double-diffused MOS transistor; ultra-low on-resistance power transistor; Conductivity; Doping; Geometry; Numerical analysis; Performance analysis; Poisson equations; Power transistors; Research and development; Semiconductor process modeling; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.8905

Filename

8905