DocumentCode
1417875
Title
A 3-terminal model for diffused and ion-implanted resistors
Author
Booth, Richard V H ; McAndrew, Colin C.
Author_Institution
AT&T Bell Labs., Allentown, PA, USA
Volume
44
Issue
5
fYear
1997
fDate
5/1/1997 12:00:00 AM
Firstpage
809
Lastpage
814
Abstract
In this paper, we present a new, physically based 3-terminal model for diffused and ion-implanted resistors. The model accounts for the effects of geometry, temperature, and bias, and includes parasitic p-n junction diodes. The junction depletion capacitances are distributed to model high-frequency behavior accurately
Keywords
CMOS integrated circuits; capacitance; ion implantation; resistors; semiconductor device models; CMOS technology; bias effects; diffused ion-implanted resistors; distributed behavior; geometry effects; high-frequency behavior; integrated resistors; junction depletion capacitances; parasitic p-n junction diodes; physically based 3-terminal model; temperature effects; Diodes; Geometry; Immune system; Land surface temperature; P-n junctions; Parasitic capacitance; Resistors; Solid modeling; Temperature dependence; Voltage;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.568043
Filename
568043
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