Title :
A 8.125–15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop
Author :
Vamvakos, Socrates D. ; Boecker, Charles ; Groen, Eric ; Wang, Aiping ; Desai, Shaishav ; Irwin, Scott ; Rao, V. ; Bottelli, Aldo ; Jawji Chen ; Xiaole Chen ; Choudhary, Prateek ; Kuo-Chiang Hsieh ; Jennings, Paul ; Haidang Lin ; Dan Pechiu ; Rao, Chethan
Author_Institution :
MoSys Inc., Santa Clara, CA, USA
Abstract :
The paper describes a 8.125-15.625 Gbps medium-reach SerDes macro for use in a networking memory system. The SerDes employs a sub-sampling ring-oscillator phase-locked loop to obtain a large frequency range with low jitter performance. In addition, the transmitter uses a modified hybrid output driver and a multi-step duty-cycle corrector. The receiver uses a BER-based calibration loop to find the set of parameters that maximizes the receiver voltage margin. The transmitter output achieves 160fs RMS jitter and 10.9ps total jitter at 15.625 Gbps with 140fs duty-cycle distortion.
Keywords :
error statistics; jitter; microwave oscillators; phase locked loops; phase locked oscillators; radio receivers; radio transmitters; BER-based calibration loop; RMS jitter; bit rate 8.125 Gbit/s to 15.625 Gbit/s; duty-cycle distortion; low jitter performance; medium-reach SerDes macro; modified hybrid output driver; multi-step duty-cycle corrector; networking memory system; receiver voltage margin; sub-sampling ring-oscillator phase-locked loop; time 10.9 ps; time 140 fs; time 160 fs; Bit error rate; Calibration; Clocks; Jitter; Noise; Phase locked loops; Voltage-controlled oscillators; Duty-cycle corrector; PLL; SerDes; phase-locked loop; sub-sampling PLL; voltage-mode transmitter;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the
Conference_Location :
San Jose, CA
DOI :
10.1109/CICC.2014.6945979
