Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceivers

Author

Westra, Jan R. ; Mulder, John ; Yi Ke ; Vecchi, Davide ; Xiaodong Liu ; Arslan, Engin ; Jiansong Wan ; Qiongna Zhang ; Wang, Shuhui ; van der Goes, Frank ; Bult, Klaas

Author_Institution

Broadcom Netherlands B.V., Bunnik, Netherlands

fYear

2014

fDate

15-17 Sept. 2014

Firstpage

1

Lastpage

8

Abstract

The speed of Ethernet over copper cables has steadily increased by a factor of 10,000 over the last four decades, from 1Mb/s in the earliest Ethernet implementations to 10Gb/s in recent systems. This paper describes the design considerations on all levels of the 10GBASE-T design hierarchy that form the basis for the implementation of highly power-efficient AFEs in full-duplex 10GBASE-T transceivers. It also shows how these considerations are implemented in a practical design. At frequencies up to 400MHz, the transceiver presented in this paper achieves >62dBc transmitter SFDR, >62dBc echo cancellation (EC) SFDR and >60dB receiver SFDR. Achieving a bit-error-rate (BER) better than 10^-15, it dissipates less than 1.75W at full 10Gb/s traffic over a 100m cable, which is the lowest power for a 10GBASE-T AFE published to date.

Keywords

local area networks; low-power electronics; radio transceivers; 10GBASE-T AFE; 10GBASE-T design hierarchy; Ethernet; bit rate 10 Gbit/s; full-duplex 10GBASE-T transceivers; low-power analog front ends; power-efficient AFE; size 100 m; Computer architecture; Electronics packaging; Hybrid power systems; Impedance; Receivers; Transceivers; Transmitters; CMOS integrated circuits; Communication systems; Digital communication; Ethernet networks;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the

Conference_Location

San Jose, CA

Type

conf

DOI

10.1109/CICC.2014.6945981

Filename

6945981