A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology

Author

Dickson, Timothy O. ; Yong Liu ; Rylov, Sergey V. ; Agrawal, Ankit ; Seongwon Kim ; Ping-Hsuan Hsieh ; Bulzacchelli, John F. ; Ferriss, Mark ; Ainspan, Herschel ; Rylyakov, A. ; Parker, Benjamin D. ; Baks, Christian ; Lei Shan ; Young Kwark ; Tierno, Jose

Author_Institution

IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2014

fDate

15-17 Sept. 2014

Firstpage

1

Lastpage

4

Abstract

A power-scalable 2-Byte I/O operating at 12-Gb/s per lane is reported. The I/O includes controllable TX driver amplitude, flexible RX equalization, and multiple deskew modes. This allows power reduction when operating over low-loss, low-skew interconnects, while at the same time supporting higher-loss channels. Measurements of a test chip fabricated in 32nm SOI CMOS technology demonstrate 1.4-pJ/b efficiency over 0.75” Megtron-6 PCB traces, and 1.9-pJ/b efficiency over 20” Megtron-6 PCB traces.

Keywords

CMOS integrated circuits; elemental semiconductors; integrated circuit interconnections; printed circuit interconnections; receivers; silicon-on-insulator; transmitters; DFE receiver; SOI CMOS technology; Si; controllable TX driver amplitude; flexible RX equalization; low-skew interconnects; multiple deskew modes; power reduction; power-scalable; size 32 nm; source-synchronous I/O; CMOS integrated circuits; Clocks; Decision feedback equalizers; Delays; Interpolation; Receivers; Transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the

Conference_Location

San Jose, CA

Type

conf

DOI

10.1109/CICC.2014.6945983

Filename

6945983