Sequential-state binary parallel adder

The process of binary addition is examined in the context of the construction of a large parallel digital computer, in which it is desired to perform fixed-point additions as rapidly as possible using current i.c. technology. The block-carry adder is shown to be the fastest method of addition previously available. Two addition algorithms are then presented, both of which involve the sum register in the addition process and allow the addition and cycle times to be significantly reduced. An adder design based on one of these algorithms is partitioned into two standard logic groups suitable for production as l.s.i. units, and reults are presented of an experimental 64-bit adder cycling every 30ns.