Advances in high-speed continuous-time delta-sigma modulators

The maximum clock rate of continuous-time ΔΣ modulators has increased dramatically over the past several years, showing that continuous-time systems can operate at higher rates than their discrete-time counterparts. This paper outlines the circuits and architectures that have led to these improvements and presents an analysis of the maximum clock rate of continuous-time ΔΣ modulators when limited by the metastability error of the internal flash ADC, resulting in a simple relationship between metastability error and SNR. A circuit simulation technique is also presented that helps analyse high-speed continuous-time systems to identify and correct non-idealities in the modulator´s transfer functions.