• DocumentCode
    141830
  • Title

    A 160 MS/s, 11.1 mW, single-channel pipelined SAR ADC with 68.3 dB SNDR

  • Author

    Tripathi, Vaibhav ; Murmann, Boris

  • Author_Institution
    Stanford Univ., Stanford, CA, USA
  • fYear
    2014
  • fDate
    15-17 Sept. 2014
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    A low-power, 160 MS/s, single-channel pipelined SAR ADC is presented. The ADC frontend employs two capacitive DACs that decouple the high-speed SAR operation from the low-noise residue generation, thereby improving both speed and power dissipation. Measured results show an SNDR of 68.3/66 dB at low frequency/Nyquist inputs, respectively, which corresponds to a FOMS of 167/164.7 dB. The converter core occupies 0.09 mm in 65-nm CMOS.
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; digital-analogue conversion; CMOS technology; DAC; digital-to-analog converters; power 11.1 nW; single-channel pipelined SAR ADC; size 0.09 mm; size 65 nm; successive approximation register analog-to-digital converter; CMOS integrated circuits; Capacitance; Capacitors; Frequency measurement; Latches; Semiconductor device measurement; Switches; A/D converters; CMOS; Pipelined SAR ADC;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the
  • Conference_Location
    San Jose, CA
  • Type

    conf

  • DOI
    10.1109/CICC.2014.6945993
  • Filename
    6945993
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=141830