Design for test of a mm-Wave ADPLL-based transmitter

The advantages of on-chip debugging capability and critical RF performance characterization are myriad in a system-on-chip (SoC) application. This paper focuses on design for test (DFT) and design for characterization (DFC) techniques applied to an all-digital phase-locked loop (ADPLL) transmitter targeting mm-wave frequencies. System snapshotting via on-chip SRAM to identify the root cause of the design deficiencies accurately is proposed. More importantly, offer the possibility of self-healing. Moreover, low-cost, built-in self test (BIST) and self characterization (BISC) of an ADPLL performance including critical building blocks (e.g., digitally controlled oscillator) are presented. RF characterization capability on chip enhances test coverage, and reduces test time and production cost. The DFT and DFC techniques are integrated and benchmarked using a 60-GHz ADPLL-based transmitter in 65-nm CMOS.