A low-leakage, hybrid ESD power supply clamp in 65nm CMOS technology

Electrostatic discharge (ESD) is a well-known problem in integrated circuits that affect its reliability, yield and cost. It is important to design ESD protection circuits that are able to prevent ESD related yield loss [1]. In this work, a 65 nm hybrid clamp that combines static and transient clamps is presented. A NMOS based ESD clamp with level converter delay is used as a transient clamp, while diode strings are used as a static clamp. Simulation and measurement results show that the proposed clamp has fast response for ESD-like events. Extensive analysis demonstrates that the clamp is stable against false triggering, power supply noise and latch up. Measurement results show that the clamp is capable of handling 1.77A of current while its leakage is only 12.9nA.