Title :
Impact of random telegraph noise on CMOS logic circuit reliability
Author :
Matsumoto, Tad ; Kobayashi, Kaoru ; Onodera, Hidetoshi
Author_Institution :
Dept. of Commun. & Comput. Eng., Kyoto Univ., Kyoto, Japan
Abstract :
The leading edge products have a feature size of 22 nm in 2014. Designing reliable systems has become a big challenge in recent years. Transistor reliability has a great impact on highly-reliable CMOS circuit operations. Random telegraph noise is one of major recent transistor reliability concerns. First, recent researches on RTN and its impact on circuits are briefly summarized. Then the impact of RTN on CMOS logic circuit reliability is described based on our results from 65 nm and 40 nm test chips. Circuit designers can change various parameters such as operating voltage, transistor size, number of logic stages and substrate bias. The impact of these parameters is clarified in view of RTN-induced CMOS logic delay uncertainty. The impact of RTN can be a serious problem even for logic circuits when they are operated under low supply voltage.
Keywords :
CMOS logic circuits; integrated circuit noise; integrated circuit reliability; random noise; CMOS circuit operation; CMOS logic circuit reliability; RTN-induced CMOS logic delay uncertainty; complementary metal-oxide-semiconductor; logic stage; operating voltage; random telegraph noise; size 22 nm; size 40 nm; size 65 mm; substrate bias; test chip; transistor reliability; transistor size; CMOS integrated circuits; Integrated circuit reliability; Logic gates; Substrates; Temperature measurement; Transistors;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the
Conference_Location :
San Jose, CA
DOI :
10.1109/CICC.2014.6945997
