Title :
A 0.010mm2 9.92psrms low tracking jitter pixel clock generator with a divider initializer and a nearest phase selector in 28nm CMOS technology
Author :
Kangyeop Choo ; Sung-Jin Kim ; Wooseok Kim ; Jihyun Kim ; Taeik Kim ; Hojin Park
Author_Institution :
Samsung Electron., Yongin, South Korea
Abstract :
A single loop low tracking jitter pixel clock generator is demonstrated in 28nm CMOS process. The proposed architecture only consists of a conventional single loop wide bandwidth fractional-N PLL and two synchronization skills which suppress the tracking jitter and bring out the delay control function like a DLL. When a 250MHz pixel clock is generated and synchronized with a 10kHz HSYNC, the measured tracking jitter is 9.92psrms. The total power consumption is 9.7mW and the silicon area is only 0.010mm2 in 28nm CMOS process.
Keywords :
CMOS integrated circuits; clocks; delay lock loops; jitter; phase locked loops; synchronisation; CMOS technology; DLL; HSYNC; complementary metal-oxide-semiconductor; delay control function; delay-locked loop; divider initializer; frequency 10 kHz; frequency 250 MHz; horizontal synchronization; nearest phase selector; phase lock loop; power 9.7 mW; power consumption; silicon area; single loop low tracking jitter pixel clock generator; single loop wide bandwidth fractional-N PLL; size 28 nm; synchronization; Bandwidth; Clocks; Delays; Jitter; Phase locked loops; Synchronization; Voltage-controlled oscillators; CMOS; DLL; HSYNC; PCG; Pixel; phase;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the
Conference_Location :
San Jose, CA
DOI :
10.1109/CICC.2014.6946005
