• DocumentCode
    141883
  • Title

    A 32-Gb/s 9.3-mW CMOS equalizer with 0.73-V supply

  • Author

    Manian, Abishek ; Razavi, Behzad

  • Author_Institution
    Electr. Eng. Dept., Univ. of California, Los Angeles, Los Angeles, CA, USA
  • fYear
    2014
  • fDate
    15-17 Sept. 2014
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    A CTLE/DFE cascade incorporates inductor nesting to reduce chip area and latch feedforward to improve the loop speed. Realized in 45-nm CMOS technology, a 32-Gb/s prototype compensates for a channel loss of 18 dB at Nyquist while providing an eye opening of 0.44 UI at BER <; 10-12.
  • Keywords
    CMOS integrated circuits; decision feedback equalisers; feedforward; inductors; CMOS equalizer; CMOS technology; CTLE/DFE; Nyquist; continuous-time linear equalizer; decision feedback equalizer; inductor nesting; latch feedforward; power 9.3 mW; size 45 nm; voltage 0.73 V; CMOS integrated circuits; CMOS technology; Decision feedback equalizers; Feedforward neural networks; Inductors; Latches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the
  • Conference_Location
    San Jose, CA
  • Type

    conf

  • DOI
    10.1109/CICC.2014.6946019
  • Filename
    6946019
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=141883