A 50–64 Gb/s serializing transmitter with a 4-tap, LC-ladder-filter-based FFE in 65-nm CMOS

This paper presents a complete 50-64 Gb/s serializing transmitter including a 4-tap equalizer. The serializer is power-optimized by using a direct 4:1 multiplexer (MUX) at the final stage with a novel 4:1 MUX circuit design. In addition, an LC-based FFE structure that eliminates the need of multiple MUXs is proposed. The FFE improves the bandwidth of the delay line and the output combiner by applying the design methodology of LC-ladder filters. By properly arranging the output combiner, the required number of inductors and the area is minimized. Designed and fabricated in 65-nm CMOS technology, the transmitter achieves a maximum data rate of 64.5 Gb/s with an energy efficiency of 3.1 pJ/bit.