A 50–64 Gb/s serializing transmitter with a 4-tap, LC-ladder-filter-based FFE in 65-nm CMOS

Author

Ming-Shuan Chen ; Yang, Chih-Kong Ken

Author_Institution

Univ. of California, Los Angeles, Los Angeles, CA, USA

fYear

2014

fDate

15-17 Sept. 2014

Firstpage

1

Lastpage

4

Abstract

This paper presents a complete 50-64 Gb/s serializing transmitter including a 4-tap equalizer. The serializer is power-optimized by using a direct 4:1 multiplexer (MUX) at the final stage with a novel 4:1 MUX circuit design. In addition, an LC-based FFE structure that eliminates the need of multiple MUXs is proposed. The FFE improves the bandwidth of the delay line and the output combiner by applying the design methodology of LC-ladder filters. By properly arranging the output combiner, the required number of inductors and the area is minimized. Designed and fabricated in 65-nm CMOS technology, the transmitter achieves a maximum data rate of 64.5 Gb/s with an energy efficiency of 3.1 pJ/bit.

Keywords

CMOS integrated circuits; LC circuits; delay lines; equalisers; feedforward; ladder filters; multiplexing equipment; pulse generators; transmitters; CMOS integrated circuit; FFE; LC ladder filter; MUX circuit design; bit rate 50 Gbit/s to 64 Gbit/s; direct multiplexer; feed forward equalizer; four tap equalizer; serializing transmitter; size 65 nm; Bandwidth; CMOS integrated circuits; Delay lines; Delays; Inductors; Multiplexing; Transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the

Conference_Location

San Jose, CA

Type

conf

DOI

10.1109/CICC.2014.6946020

Filename

6946020