A 12.5-Gb/s self-calibrating linear phase detector-based CDR using 0.18μm SiGe BiCMOS

Author

Walker, Julian ; Kenney, John G. ; Bankman, Jesse ; Chen, T. ; Harston, Steve ; Lawas, Kenneth ; Lewine, Andrew ; Soenneker, Richard ; St. Germain, Michael ; Titus, Ward ; Wang, A. Yongsheng ; Tam, Kimo

Author_Institution

Analog Devices, San Jose, CA, USA

fYear

2014

fDate

15-17 Sept. 2014

Firstpage

1

Lastpage

4

Abstract

A 12.5 Gb/s half-rate clock and data recovery (CDR) circuit is described. The CDR uses a half-rate linear phase detector (LPD) which minimizes the number of latches required. To correct for static phase offsets (SPO) that inevitably result from variations in analog circuit parameters, a calibration scheme is used on startup. Measured high-frequency jitter tolerance is improved by up to 0.2 UIpp through this calibration. Power for the CDR, excluding the PLL and I/O circuits, is 82 mW at 12 Gb/s.

Keywords

BiCMOS integrated circuits; Ge-Si alloys; calibration; clock and data recovery circuits; phase detectors; BiCMOS; CDR; SiGe; bit rate 12 Gbit/s; half rate clock and data recovery circuit; half-rate linear phase detector; latch minimization; power 82 mW; self-calibrating linear phase detector; size 0.18 mum; static phase offset correction; BiCMOS integrated circuits; Calibration; Clocks; Detectors; Jitter; Latches; Timing; BiCMOS integrated circuits; clock and data recovery (CDR); delay-locked-loop (DLL);

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the

Conference_Location

San Jose, CA

Type

conf

DOI

10.1109/CICC.2014.6946022

Filename

6946022