• DocumentCode
    141891
  • Title

    A 6.5Mb/s to 11.3Gb/s continuous-rate clock and data recovery

  • Author

    Kenney, Jack ; Chen, T. ; DeVito, Larry ; Dalton, Declan ; McCracken, Stuart ; Soenneker, Richard ; Titus, Ward ; Weigandt, Todd

  • Author_Institution
    Analog Devices Inc., Somerset, NJ, USA
  • fYear
    2014
  • fDate
    15-17 Sept. 2014
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    A continuous-rate CDR based upon a digital dual delay/phase locked loop is reported. This CDR is implemented in 0.13μm CMOS and operates from 6.5Mb/s to 11.3Gb/s. It exceeds all SONET jitter specifications from OC-3 to OC-192, with random jitter of 452fs at 9.95Gb/s. The die area is 2×2mm2, and is implemented in a 24-pin LFCSP.
  • Keywords
    CMOS digital integrated circuits; clock and data recovery circuits; digital phase locked loops; 24-pin LFCSP; CMOS process; SONET jitter specifications; bit rate 6.5 Mbit/s to 11.3 Gbit/s; continuous-rate CDR; continuous-rate clock and data recovery; digital dual delay-phase locked loop; random jitter; size 0.13 mum; time 452 fs; Arrays; Bandwidth; Clocks; Detectors; Jitter; Phase locked loops; Phase shifters;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the
  • Conference_Location
    San Jose, CA
  • Type

    conf

  • DOI
    10.1109/CICC.2014.6946023
  • Filename
    6946023
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=141891