n-p-n Array Yield Improvement in a 0.18-μm Deep Trench SiGe BiCMOS Process

The deep trench (DT) process module shows a strong impact on SiGe BiCMOS n-p-n array yield. DT liner oxidation introduces large tensile stress at the top of DT corners and in the vicinity of intrinsic SiGe base/collector regions. The increased tensile stress can result in dislocations in silicon. By replacing the 100-nm wet oxidation DT liner with a TEOS deposition liner, n-p-n array collector-emitter leakage yield can be improved from 64% to 94% in the investigated 0.18-μm DT SiGe BiCMOS process, comparable to the yield of a non-DT low-cost SiGe BiCMOS process.