A 1.1V 2y-nm 4.35Gb/s/pin 8Gb LPDDR4 mobile device with bandwidth improvement techniques

Author

Keunsoo Song ; Sangkwon Lee ; Dongkyun Kim ; Youngbo Shim ; Sangil Park ; Bokrim Ko ; Duckhwa Hong ; Yongsuk Joo ; Wooyoung Lee ; Yongdeok Cho ; Wooyeol Shin ; Jaewoong Yun ; Hyengouk Lee ; Jeonghun Lee ; Eunryeong Lee ; Jaemo Yang ; Haekang Jung ; Namkyu

Author_Institution

Jinkook Kim SK hynix, Icheon, South Korea

fYear

2014

fDate

15-17 Sept. 2014

Firstpage

1

Lastpage

4

Abstract

The demands on higher bandwidth with reduced power consumption in mobile market are driving mobile DRAM to have advanced design techniques. Proposed LPDDR4 in this paper achieves over 30% improved power efficiency and over 4.3Gbps data rate with 1.1V supply voltage. These are challenging target comparing with that of LPDDR3. This works includes various techniques including multi-channel per die, various trainings, low swing interface, DQS and clock frequency dividing, internal reference voltage for data and command-address signals and so on. This chip was fabricated in a 3-metal 2y-nm DRAM CMOS process.

Keywords

CMOS integrated circuits; DRAM chips; clocks; low-power electronics; 3-metal 2y-nm DRAM CMOS process; LPDDR4 mobile device; bandwidth improvement techniques; bit rate 4.3 Gbit/s; clock frequency; command-address signals; internal reference voltage; low swing interface; mobile DRAM; mobile market; power consumption; storage capacity 8 Gbit; various trainings; voltage 1.1 V; Bandwidth; Clocks; Computer aided software engineering; Frequency conversion; Random access memory; Timing; Training; DRAM; LPDDR4; dram interface; memory architecture; training;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the

Conference_Location

San Jose, CA

Type

conf

DOI

10.1109/CICC.2014.6946032

Filename

6946032