Title :
Optimization on Layout Style of ESD Protection Diode for Radio-Frequency Front-End and High-Speed I/O Interface Circuits
Author :
Yeh, Chih-Ting ; Ker, Ming-Dou ; Liang, Yung-Chih
Author_Institution :
Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
6/1/2010 12:00:00 AM
Abstract :
The diode operated in forward-biased condition has been widely used as an effective on-chip electrostatic discharge (ESD) protection device at radio-frequency (RF) front-end and high-speed input/output (I/O) pads due to the small parasitic loading effect and high ESD robustness in CMOS integrated circuits (ICs). This work presents new ESD protection diodes drawn in the octagon, waffle-hollow, and octagon-hollow layout styles to improve the efficiency of ESD current distribution and to reduce the parasitic capacitance. The measured results confirmed that they can achieve smaller parasitic capacitance under the same ESD robustness level as compared to the stripe and waffle diodes, especially for the diodes drawn in the hollow layout style. Therefore, the signal degradation of RF and high-speed transmission can be reduced because of smaller parasitic capacitance from the new proposed diodes.
Keywords :
CMOS integrated circuits; electrostatic discharge; integrated circuit layout; integrated circuit reliability; optimisation; CMOS integrated circuits; ESD current distribution; ESD protection diode; electrostatic discharge; forward-biased condition; octagon layout; octagon-hollow layout; optimization; parasitic capacitance; parasitic loading effect; radio-frequency front-end I/O interface circuits; radio-frequency high-speed I/O interface circuits; waffle-hollow layout; Diode; electrostatic discharge (ESD); layout; radio-frequency (RF);
Journal_Title :
Device and Materials Reliability, IEEE Transactions on
DOI :
10.1109/TDMR.2010.2043433