DocumentCode :
141966
Title :
The effect of Shallow Trench Isolation improvement on program disturb response in 20 nm NAND flash technology
Author :
Chandrasekaran, S. ; Venkatesan, S. ; Eagle, Oliver H. ; Iyengar, Vikram V. ; Reyes, Art B. ; Gowda, Srivardhan S.
Author_Institution :
Intel Micron Flash Technol. LLC, Lehi, UT, USA
fYear :
2014
fDate :
18-18 April 2014
Firstpage :
1
Lastpage :
4
Abstract :
In this paper, the effect of Shallow Trench Isolation (STI) degradation on program disturb is studied. It is reported that trench isolation is compromised with non-uniformity in trench depth leading to increased boost loss through field isolation leakage. This degradation in boost loss further leads to elevated program disturb fails. Further investigation identified three factors namely-STI depth Imbalance, channel enhancement implant and STI etch process with improved cross wafer profile, which have been optimized to successfully alleviate Program Disturb fails.
Keywords :
NAND circuits; etching; isolation technology; NAND flash technology; STI depth imbalance; STI etch process; boost loss; channel enhancement implant; field isolation leakage; program disturb response; shallow trench isolation; size 20 nm; trench depth; wafer profile; Arrays; Degradation; Flash memories; Implants; Measurement; Process control; Reliability; Active Area (AA); Active Area Aspect Ratio (AAAR); Bit Line (BL); Critical Dimension (CD); Field isolation; Program Disturb (PD); STI Depth Imbalance; Shallow Trench Isolation (STI); Threshold Voltage (Vt); Word Line (WL);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronics And Electron Devices (WMED), 2014 IEEE Workshop On
Conference_Location :
Boise, ID
ISSN :
1947-3834
Print_ISBN :
978-1-4799-2222-2
Type :
conf
DOI :
10.1109/WMED.2014.6818718
Filename :
6818718
Link To Document :
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