Advanced modeling and simulation of state-of-the-art high-speed I/O interfaces

Today´s high-speed I/O interfaces demand extensive modeling and simulation to: design optimal equalization to compensate channel loss, compare different clocking schemes, verify functionalities of digital calibration/adaptation loops. For effective system-level performance analysis, it is important to understand the key modeling requirements for each of the link components, and to use an efficient simulator that can achieve both high accuracy and fast speed.