Configurable incremental sigma-delta ADC for DC measure and audio conversion

A configurable three-level sigma-delta ADC for both DC measurement and audio conversion is implemented in a 40 nm CMOS process. It employs a switch-capacitor level shifter to increase the DC input range. Dynamic Element Matching (DEM), typically used in traditional multilevel feedback DAC, is avoided by setting proper common-mode (CM) voltage. Using a time-sharing technique, the three-level quantizer uses only one set of summer/comparator to save power and area. A simple analytical formula that accurately predicts DC measurement incremental noise is proposed to avoid overdesign. The ADC achieves 83 dB SNR and 79 dB peak SNDR for a 1 kHz audio input, and 11-bit accuracy for DC measurements with 100 kHz conversion rate, at the power of 0.5 mW.