Independent N and P process monitors for body bias based process corner correction

Process monitors that independently sense on-die PMOS and NMOS as-fabricated performance are presented. The monitors provide digital outputs, making them easily integrated blocks on SOC designs. We present two monitor approaches, one primarily analog and one primarily digital, applied to both logic circuits and SRAM, which may require different optimal body biases for best operation. The monitors correctly sense the die as-fabricated process corners on 55-nm test die, demonstrated on FF, FS, TT, SF SS corner skew lots. Experimentally measured performance and power correction is demonstrated for digital circuits, as well as parametric yield correction for SRAMs. Logic ring oscillators demonstrate 74% reduction in standard deviation for delay and leakage with monitor specified body biases. Similar improvement is demonstrated on embedded microprocessors. Finally, 55% and 72% reduction in SRAM read current variability and leakage, respectively, is also shown.