Title :
A tri-stack buck converter with gate coupling control (GCC) and quasi adaptive dead time control (QADTC)
Author :
Jun-Han Choi ; Sang-hui Park ; Gyu-Hyeong Cho
Author_Institution :
KAIST, Daejeon, South Korea
Abstract :
A DC-DC buck converter handling three times the nomal transistors´ nominal voltage is implemented with 1.8V I/O devices in a 65nm digital process with the aim of creating an analog intellectual property that is robust, easily reconfigurable and cost effective. Moreover, the maximum current density and the efficiency of the powering block reach to 1.28A/mm2 and 93.8%, respectively, with the help of the high mobility of the transistor.
Keywords :
CMOS digital integrated circuits; DC-DC power convertors; adaptive control; current density; digital circuits; transistor circuits; DC-DC buck converter; GCC; I-O devices; QADTC; current density; digital process; gate coupling control; powering block; quasi adaptive dead time control; size 65 nm; tristack buck converter; voltage 18 V; Batteries; Capacitors; Couplings; Layout; Logic gates; MOS devices; Rails; Voltage tolerant; adaptive dead time control; gate coupling; tolerant buck; triple stack;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the
Conference_Location :
San Jose, CA
DOI :
10.1109/CICC.2014.6946093
