Innovative practices session 1C: Existing/emerging low power techniques

Low-power testing has become a need for modern designs due to rapid increasing of power density with further shrinking of feature size into nanoscale designs. In spite of low-power design efforts and low-power ATPG adopted in common test flows, excessive power dissipation and instant peak current cannot be necessarily avoided during test application. There is a need for fast peak power detection for test vectors. The test industry lacks such efficient solution. In this work, we propose a fast test power analysis methodology. By reading and processing layout data and other supporting files such as parasitic files, the proposed analysis engine performs a simplified power grid analysis with layout partition and provides following power results for each test cycle: switching activity, absolute power, hot spot contour map, absolute current estimation on power pads. The proposed flow was verified on industry designs and proved to be very efficient than using commercial power sign-off solutions for test power analysis.