Reducing computational overhead of flash translation layer with hashed page tables

NAND flash memory is lightweight, small, shock-resistant, silent, and low in energy consumption. Thus it is widely used as a storage medium of various block devices such as SD cards, USB drives, and more recently, solid-state drives. However, given that it does not support the overwrite function, NAND-based block devices embed a firmware called Flash Translation Layer (FTL) to emulate the block device interface. The performance of a NAND-based block device is mainly determined by the efficiency of FTL as well as the performance of the NAND flash memory itself. Most previous work focused on, and succeeded in, significantly reducing the number of NAND operations such as write and erase. However, the overall performance was not substantially improved because of the enormous computational overhead of operating FTL. The overhead mainly stems from a linear search of target sectors for the entire log block space. This work presents a method to reduce the number of linear searches with the help of a hashed page table. A trace-driven simulation shows that the hashed page table effectively reduces the computational overhead of the existing scheme. The total elapsed time decreases by up to 46% compared to the original FAST scheme, and the impact of the CPU frequency on the performance of NAND-based block devices is also reduced. The hashed page table is anticipated to make FAST-like schemes feasible for NAND-based block devices which embed low-speed controllers.